Title :
Circuit behavior modeling and compact testing performance evaluation
Author :
Yih, Jih-Shyr ; Mazumder, Pinaki
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
fDate :
1/1/1991 12:00:00 AM
Abstract :
A realistic modeling of circuit output error patterns with random test inputs is suggested. The model can be used as the basis for accurate evaluation of the probability of aliasing in compact testing. For several example compression techniques, the following aspects are investigated: identification of the error patterns that cause aliasing; asymptotic effectiveness analysis; and comparative simulation study with a limited number of random test vectors applied
Keywords :
data compression; digital simulation; logic testing; probability; random processes; aliasing; asymptotic effectiveness analysis; circuit behaviour modelling; compact testing; comparative simulation; data compression; identification; logic testing; output error patterns; polynomial divisions; probability; random test inputs; transition counting; Cause effect analysis; Circuit faults; Circuit testing; Computer errors; Data compression; Electrical fault detection; Fault detection; Performance analysis; Polynomials; Shift registers;
Journal_Title :
Solid-State Circuits, IEEE Journal of
