Interconnects for Novel State Variables: Performance Modeling and Device and Circuit Implications

Fundamental laws of physics will severely limit the “scaling” of silicon FETs beyond the 2020 technology roadmap. There is a need to look for an alternate switching paradigm that can overcome the limitations of the current Si FET technology. Nanoelectronic switches that work with state variables other than electron charge are being investigated by researchers. Some of these post-CMOS technologies hold the promise to extend Moore´s law beyond the technology year 2020. Any new logic that aims at replacing the CMOS logic must be complemented with an interconnect technology that can transmit information encoded in the new computational variable between different physical locations of the chip. The focus of this paper is to map new logic technology with its respective interconnect technology. In this paper, comprehensive physical models of transport mechanisms that can be utilized for novel state variable transport through these novel interconnects are developed. An upper bound on speed of these interconnects is obtained, and a comparison is drawn between novel and CMOS interconnects. A comparison of delay of novel interconnects with CMOS interconnects provides important insights into the material, device, and circuit implications of these new interconnects.