Title :
New strategies for fast ADC circuits
Author :
Dighe, A.M. ; Kelkar, A.R.
Author_Institution :
Dept. of Electron. Eng., Visvesvaraya Regional Coll. of Eng., Nagpur, India
fDate :
12/1/1990 12:00:00 AM
Abstract :
A modified strategy for successive approximation is discussed. A four-bit multilevel converter of one-cycle conversion time is first described. Approximation is carried over at two levels handling two bits at a time. This results in a relative speed improvement of five times over the conventional method for the four-bit scheme. The four-bit multilevel converter is modified for flash conversion. Experimental results for the four-bit flash converter are presented. Eight-bit converters, as extensions of the four-bit schemes presented, are also proposed. Practical results of the four-bit multilevel flash converter display good linearity. The worst-case conversion time was found to be about 650 ns
Keywords :
analogue-digital conversion; 650 ns; eight-bit converters; flash conversion; four-bit multilevel converter; linearity; one-cycle conversion time; successive approximation; worst-case conversion time; Analog-digital conversion; Circuits; Clocks; Encoding; Latches; Logic; Vents;
Journal_Title :
Instrumentation and Measurement, IEEE Transactions on
