An algorithm analog-to-digital converter using unity-gain buffers

Author

Ogawa, Satomi ; Watanabe, Kenzo

Author_Institution

Res. Inst. of Electron., Shizuoka Univ., Hamamatsu, Japan

Volume

39

Issue

6

fYear

1990

fDate

12/1/1990 12:00:00 AM

Firstpage

886

Lastpage

889

Abstract

An algorithmic stage for bipolar 1-b analog-to-digital (A/D) conversion using a unity-gain buffer is proposed. Cyclic and pipeline A/D converter architectures using this stage iteratively or in cascade are also described. Error analysis and SPICE simulations show that a conversion accuracy higher than 8-b and a conversion rate up to 10 Mb/s are attainable with presently available 3-μm CMOS technologies. Video frequency operation is also possible with finer linewidths. The component requirement is minimum, and thus it is best suited for an analog interface in application-specific integrated circuits (ASIC). A prototype cyclid A/D converter built using discrete components confirms the principles of operation

Keywords

CMOS integrated circuits; analogue-digital conversion; application specific integrated circuits; digital simulation; error analysis; pipeline processing; 3 micron; ASIC; CMOS technologies; SPICE simulations; algorithm analog-to-digital converter; analog interface; cyclic converter architecture; error analysis; pipeline A/D converter architectures; unity-gain buffers; Analog-digital conversion; Analytical models; Application specific integrated circuits; CMOS technology; Error analysis; Frequency; Integrated circuit technology; Iterative algorithms; Pipelines; SPICE;

fLanguage

English

Journal_Title

Instrumentation and Measurement, IEEE Transactions on

Publisher

ieee

ISSN

0018-9456

Type

jour

DOI

10.1109/19.65790

Filename

65790