Dual-period self-refresh scheme for low-power DRAM´s with on-chip PROM mode register

Author

Idei, Youji ; Shimohigashi, Katsuhiro ; Aoki, Masakazu ; Noda, Hiromasa ; Iwai, Hidetoshi ; Sato, Katsuyuki ; Tachibana, Tadashi

Author_Institution

Integrated Circuits Div., Hitachi Ltd., Tokyo, Japan

Volume

33

Issue

2

fYear

1998

fDate

2/1/1998 12:00:00 AM

Firstpage

253

Lastpage

259

Abstract

A dual-period self-refresh (DPS-refresh) scheme for low-power DRAM´s is proposed. Word lines are classified into two groups according to retention test data which are stored in a PROM mode register implemented in the chip periphery. The word lines are controlled individually by combining the memory-mat-select signal and the classification signal from the PROM register. The effective refresh period can be extended by four to six times compared to the conventional self-refresh period. Data-retention current of a 64-Mb DRAM test chip featuring the proposed DPS-refresh scheme is reduced to half the conventional self-refresh current without considerable area penalty

Keywords

DRAM chips; PROM; 64 Mbit; classification signal; data-retention current reduction; dual-period self-refresh scheme; effective refresh period; low-power DRAM; memory-mat-select signal; onchip PROM mode register; word lines; Automatic testing; Circuit testing; Decoding; Fuses; PROM; Power generation; Random access memory; Redundancy; Registers; Space technology;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.658627

Filename

658627