Effect of floating-body charge on SOI MOSFET design

Author

Wei, Andy ; Sherony, Melanie J. ; Antoniadis, Dimitri A.

Author_Institution

Microsystems Technol. Lab., MIT, Cambridge, MA, USA

Volume

45

Issue

2

fYear

1998

fDate

2/1/1998 12:00:00 AM

Firstpage

430

Lastpage

438

Abstract

This work presents a new method for assessing the effect of floating-body charge on a fully- and partially-depleted Silicon-on-Insulator (SOI) MOSFET device design space. Floating-body effects under transient conditions are incorporated into the device design parameters threshold voltage V_T and off-current I_0FF using calibrated two-dimensional (2-D) device simulation. Simulation methodology which reveals the worst-case bounds of the device design parameters, from idle to switching-steady-state, is presented and applied to a CMOS inverter example. Using this methodology, the worst-case shifts in V_T and I_0FF due to hysteretic floating-body charge are quantified for devices in L _eff=0.2- and 0.1-μm design spaces. Methods to reduce floating-body effects are discussed including a demonstration of how reducing the effective bulk carrier lifetime widens the 0.1-μm design space

Keywords

CMOS integrated circuits; MOSFET; carrier lifetime; equivalent circuits; semiconductor device models; silicon-on-insulator; 0.1 micron; 0.2 micron; 2D device simulation; SOI MOSFET design; Si; bulk carrier lifetime reduction; device design parameters; floating-body charge effect; fully-depleted device; hysteretic floating-body charge; offcurrent; partially-depleted device; threshold voltage; transient conditions; Dielectrics; Hysteresis; Impact ionization; MOSFET circuits; Propagation delay; Semiconductor diodes; Silicon on insulator technology; Space charge; Threshold voltage; Two dimensional displays;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.658677

Filename

658677