Influence of asymmetric/symmetric source/drain region on asymmetry and mismatch of CMOSFET´s and circuit performance

Author

Ohzone, Takashi ; Miyakawa, Tetsu ; Matsuda, Toshihiro ; Yabu, Toshiki ; Odanaka, Shinji

Author_Institution

Dept. of Electron. & Inf., Toyama Prefectural Univ., Japan

Volume

45

Issue

2

fYear

1998

fDate

2/1/1998 12:00:00 AM

Firstpage

529

Lastpage

537

Abstract

Experimental results on asymmetry and mismatch (A&M) characteristics are discussed for 0.5-μm surface-channel n-MOSFETs and buried-channel p-MOSFETs fabricated with four ion-implantation methods and designed with a conventional and a side-by-side layout. The side-by-side layout is useful to improve A&M caused by source/drain asymmetry in MOSFETs with a one-sided 7°-implantation method. The symmetric 7°×4-implantation method gives good A&M characteristics of n- and p-MOSFET´s with the both layouts. According to the circuit performance of ring oscillators, the ion-implantation method is correlated to supply-current/oscillation-frequency/delay-power product and substrate current. The symmetric 7°×4-implantation method is the most preferable in terms of A&M and punchthrough immunity of CMOSFET as well as circuit performance

Keywords

CMOS integrated circuits; MOSFET; integrated circuit layout; ion implantation; 0.5 micron; CMOSFET; NMOSFET; PMOSFET; asymmetric/symmetric source/drain region; asymmetry/mismatch characteristics; buried-channel p-MOSFET; circuit performance; delay-power product; electrical characteristics mismatch; ion-implantation methods; oscillation-frequency; punchthrough immunity; side-by-side layout; substrate current; supply-current; surface-channel n-MOSFET; CMOS process; CMOSFETs; Circuit optimization; Circuit testing; Degradation; Doping; Electric variables; MOSFET circuits; Random access memory; Ring oscillators;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.658690

Filename

658690