• DocumentCode
    1306674
  • Title

    Self-timed system design technique

  • Author

    Unnikrishnan, R. ; Gupta, Arpan

  • Author_Institution
    Dept. of Electr. Eng., Rochester Inst. of Technol., NY, USA
  • Volume
    26
  • Issue
    5
  • fYear
    1990
  • fDate
    3/1/1990 12:00:00 AM
  • Firstpage
    284
  • Lastpage
    286
  • Abstract
    A new technique for the design of self-timed systems using a modified PCVSL (Precharged Cascode Voltage Switch Logic) circuit and a new handshaking protocol is presented. This technique allows different data to be stored and computed in consecutive PCVSL pipeline stages simultaneously, resulting in a significant saving in silicon area and speed-up in fall-through delay.
  • Keywords
    digital circuits; logic design; pipeline processing; protocols; timing circuits; PCVSL pipeline stages; Precharged Cascode Voltage Switch Logic; fall-through delay speed up; handshaking protocol; self-timed system design technique; silicon area;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19900188
  • Filename
    82614
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1306674