Latchup in CMOS technologies

This paper shows how a conceptually simple definition of a PNPN structure´s blocking state is also a precise statement of when latchup occurs, a statement that leads to a concise (there are no fitting parameters), experimentally verified equation for sivitching current. This paper also categorizes the operational PNPN configurations for various triggering modes and shows how they reduce to two simply analyzed cases. It also discusses latchup avoidance techniques from the perspective of the new latchup criterion.