Sub-word parallelism in digital signal processing

Author

Fridman, Jose

Author_Institution

Analog Devices Inc., Norwood, MA, USA

Volume

17

Issue

2

fYear

2000

fDate

3/1/2000 12:00:00 AM

Firstpage

27

Lastpage

35

Abstract

We deal with parallelism at the data level. We describe an implementation of the architectural technique called sub-word parallelism (SWP), which increases parallelism at the data-element-level by means of partitioning a processor´s data path. The specific implementation we focus on is based on the TigerSHARC DSP architecture, developed at Analog Devices, Inc. As a result of SWP, the same data path and computation units perform more than one computation on an N-element composite word. This composite word consists of more than one adjacent sub-words. SWP is quite common and exists in production versions of most major general-purpose microprocessors. We also present an implementation of an FIR filter in the TigerSHARC using data-level SWP as an example

Keywords

FIR filters; digital filters; digital signal processing chips; parallel architectures; Analog Devices; FIR filter; TigerSHARC DSP architecture; composite word; computation units; data level parallelism; data path partitioning; data-element-level parallelism; data-level SWP; digital signal processing; general-purpose microprocessors; sub-word parallelism; Digital signal processing;

fLanguage

English

Journal_Title

Signal Processing Magazine, IEEE

Publisher

ieee

ISSN

1053-5888

Type

jour

DOI

10.1109/79.826409

Filename

826409