Matching analysis of deposition defined 50-nm MOSFET´s

NMOS- and PMOS-transistors with geometries down to 50 nm are fabricated by conventional optical lithography using a deposition- and etchback technique for masking the polysilicon layer. The significant process steps, especially the specific gate definition process and the doping of the source/drain-extensions, are explained. These transistors are then characterized and proceedings to increase their performance are suggested. The local and global matching of sub-100-nm transistors is analyzed by a large number of measurements and compared to typical literature values and simulations. The law of area (σV_T∝1/√(W·L)) is confirmed for device dimensions from W/L=10 μm/1 μm down to W/L=1 μm/50 nm. Based on this law of area, considerations to reduce the threshold voltage scattering for sub-100-nm transistors will be suggested