Modeling of gate line delay in very large active matrix liquid crystal displays

Author

Zhang, Qing ; Shen, D.S. ; Gleskova, H. ; Wagner, S.

Author_Institution

Dept. of Electr. & Comput. Eng., Alabama Univ., Huntsville, AL, USA

Volume

45

Issue

1

fYear

1998

fDate

1/1/1998 12:00:00 AM

Firstpage

343

Lastpage

345

Abstract

With standard inverted-staggered amorphous silicon based TFT´s, the size of active matrix liquid crystal displays is restricted by the RC time constant of the gate conductor. This RC delay can be reduced considerably by connecting the gate line through via holes to a bus run on the back side of the substrate. We use the SPICE model to examine the relationship between the RC delay and all important circuit parameters. The results show that with a low-resistance back line and only a few via holes per line, the delay can be reduced by nearly a factor of ten

Keywords

RC circuits; SPICE; cascade networks; delays; liquid crystal displays; AMLCD; RC delay; RC time constant; RC transmission line; SPICE model; circuit model; circuit parameters; gate line delay modeling; low-resistance back line; substrate back side; two-port network cascade; very large active matrix liquid crystal displays; Active matrix liquid crystal displays; Amorphous silicon; Conductors; Delay effects; Delay lines; Joining processes; Power transmission lines; SPICE; Substrates; Voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.658856

Filename

658856