• DocumentCode
    1307596
  • Title

    A New Grounding Scheme to Reduce the Electromagnetic Emission of Smart-Power System-on-Chips

  • Author

    Fiori, Franco ; Merlin, Marco

  • Author_Institution
    Electron. Dept., Politec. di Torino, Torino, Italy
  • Volume
    27
  • Issue
    1
  • fYear
    2012
  • Firstpage
    224
  • Lastpage
    234
  • Abstract
    This paper focuses on the electromagnetic emissions of smart-power integrated systems that include analog, digital, and power sections. With reference to common high-voltage CMOS technology processes, it is shown that the switching noise of digital core blocks can propagate to the power sections through the silicon substrate they share. Such disturbances feed the printed circuit board traces and cables connected to the IC power section, which behave like parasitic antennas, and unwanted electromagnetic emissions are experienced. A generic integrated system fabricated with a planar CMOS technology process is considered and the propagation of digital switching noise is analyzed referring to a system level equivalent circuit, which comprises a substrate model and an IC package model. Based on this, the circuit parameters that affect the propagation of the switching noise are highlighted and a new grounding scheme, which reduces the substrate parasitic coupling in smart-power system-on-chip, is proposed. Its effectiveness is proved through computer simulations and experimental tests.
  • Keywords
    CMOS integrated circuits; earthing; electromagnetic interference; elemental semiconductors; integrated circuit noise; integrated circuit packaging; silicon; system-on-chip; IC package model; IC power section; Si; computer simulations; digital core blocks; digital switching noise propagation; electromagnetic emission; equivalent circuit; high-voltage CMOS technology processes; parasitic antennas; planar CMOS technology; printed circuit board; smart-power integrated systems; smart-power system-on-chips; substrate parasitic coupling; Electromagnetics; Integrated circuit modeling; Logic gates; Substrates; Switching circuits; System-on-a-chip; Application-specific ICs (ASICs); electromagnetic compatibility (EMC); electromagnetic emission; front end ICs; smart power; substrate coupling; switching noise; system-on-chip (SoC);
  • fLanguage
    English
  • Journal_Title
    Power Electronics, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0885-8993
  • Type

    jour

  • DOI
    10.1109/TPEL.2010.2068312
  • Filename
    5559480