DocumentCode
1307743
Title
Improved circuit implementation of adaptive phase comparators
Author
Haartsen, J.C. ; den Dulk, Richard C.
Author_Institution
Dept. of Electr. Eng., Delft Univ. of Technol.
Volume
24
Issue
10
fYear
1988
fDate
5/12/1988 12:00:00 AM
Firstpage
574
Lastpage
576
Abstract
An improved implementation of an adaptive phase comparator circuit is presented. The adaptive phase comparator can be thought of as a five-cell up-down counter that is bounded in both the outermost cells. A new design concept leads to a circuit with a higher maximum operation frequency while maintaining the basic requirements of handling coincident input signals and absence of intermediate states. The circuit is based on the application of a number of identical logic elements, which are placed in a ring structure
Keywords
counting circuits; phase comparators; sequential circuits; adaptive phase comparator circuit; coincident input signals; design concept; five-cell up-down counter; logic elements; maximum operation frequency; ring structure; sequential circuit;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
Filename
8267
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