Title :
Low-power direct digital frequency synthesis for wireless communications
Author :
Bellaouar, Abdellatif ; O´Brecht, Michael S. ; Fahim, Amr M. ; Elmasry, Mohamad I.
Author_Institution :
Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
fDate :
3/1/2000 12:00:00 AM
Abstract :
A low-power direct digital frequency synthesizer (DDFS) architecture is presented. It uses a smaller lookup table for sine and cosine functions compared to already existing systems with a minimum additional hardware. Only 16 points are stored in the internal memory implemented in ROM (read-only memory). The full computation of the generated sine and cosine is based on the linear interpolation between the sample points. A DDFS with 60-dBc spectral purity 29-Hz frequency resolution, and 9-bit output data for sine function generation is being implemented in 0.8-/spl mu/m CMOS technology. Experimental results verify that the average power dissipation of the DDFS logic is 9.5 mW (at 30 MHz, 3.3 V).
Keywords :
CMOS digital integrated circuits; cellular radio; direct digital synthesis; interpolation; land mobile radio; low-power electronics; table lookup; 0.8 micron; 3.3 V; 30 MHz; 9.5 mW; CMOS technology; average power dissipation; cosine functions; direct digital frequency synthesis; frequency resolution; internal memory; linear interpolation; lookup table; sine function generation; sine functions; spectral purity; wireless communications; CMOS logic circuits; CMOS technology; Clocks; Computer architecture; Frequency synthesizers; Hardware; Read only memory; Table lookup; Very large scale integration; Wireless communication;
Journal_Title :
Solid-State Circuits, IEEE Journal of
