Bus architecture of a system on a chip with user-configurable system logic

A bus architecture that provides high performance while scaling across a range of chip sizes is described. The system on a chip design in which it has been implemented includes both a dedicated processor with a set of embedded system peripherals and system support logic that may be reconfigured by a user in the field. Multiple masters and slaves are provided for in the architecture and included in the dedicated portion of this chip. Designers configure additional bus slave peripherals and support functions in the programmable logic. Dedicated structures extend the bus throughout the user-configurable system logic. The bus is pipelined, uses OR gates, and has separate read and write data. The bus pipeline registers are distributed to provide predictable performance and a synchronous interface to the designer. Bus protocol decoders are also distributed throughout the logic. These protocol decoders handle the complexities of pipelining for the designer. Virtual bus sockets provide all of the physical signals necessary to interface registers to the bus for single-cycle read and write transactions. The physical characteristics and design methods involved in the design of this system on a chip as well as those of the application environment all influenced the design tradeoffs in this architecture.