Title :
A solution methodology for exact design space exploration in a three-dimensional design space
Author :
Chaudhuri, Samit ; Blthye, S.A. ; Walker, Robert A.
Author_Institution :
Dept. of Electr. Comput. & Syst. Eng., Rensselaer Polytech. Inst., Troy, NY, USA
fDate :
3/1/1997 12:00:00 AM
Abstract :
This paper describes an exact solution methodology, implemented in Rensselaer´s Voyager design space exploration system, for solving the scheduling problem in a three-dimensional (3-D) design space: the usual two-dimensional (2-D) design space (which trades off area and schedule length), plus a third dimension representing clock length. Unlike design space exploration methodologies which rely on bounds or estimates, this methodology is guaranteed to find the globally optimal solution to a 3-D scheduling problem. Furthermore, this methodology efficiently prunes the search space, eliminating provably inferior design points through the following: 1) a careful selection of candidate clock lengths and 2) tight bounds on the number of functional units or on the schedule length. Both chaining and multicycle operations are supported.
Keywords :
VLSI; circuit optimisation; clocks; high level synthesis; integrated circuit design; scheduling; 3D design space; Rensselaer´s Voyager design space exploration system; candidate clock lengths; chaining; clock length; exact design space exploration; functional units; globally optimal solution; high level synthesis; multicycle operations; schedule length; scheduling problem; solution methodology; three-dimensional design space; Algorithm design and analysis; Clocks; Computer science; Control system synthesis; Delay; Design methodology; High level synthesis; Process design; Space exploration; Two dimensional displays;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on