Charge collection in submicron CMOS/SOI technology

Author

Musseau, O. ; Ferlet-Cavrois, V. ; Campbell, A.B. ; Knudson, A.R. ; Stapor, W.J. ; McDonald, P.T. ; Pelloie, J.L. ; Raynaud, C.

Author_Institution

CEA, Centre d´´Etudes de Bruyeres-le-Chatel, France

Volume

44

Issue

6

fYear

1997

fDate

12/1/1997 12:00:00 AM

Firstpage

2124

Lastpage

2133

Abstract

We present experimental measurements of charge collection spectroscopy from high energy ion strikes in submicron CMOS/SOI devices. Due to the specific structure of SOI technology, with symmetrical source and drain junctions, a direct equivalence between upset mechanism and charge collection is established. The bipolar mechanism, responsible for the amplification of the deposited charge is discussed based on 2D device simulations. Based on the experimental data we determine qualitatively the influence of transistor geometry on the bipolar gain. Finally the limits of the usual SEU concepts (LET threshold and cross section) are discussed for scaled devices

Keywords

CMOS integrated circuits; ion beam effects; silicon-on-insulator; 2D simulation; LET threshold; SEU; bipolar gain; charge amplification; charge collection spectroscopy; cross section; high energy ion strike; scaled device; submicron CMOS/SOI technology; transistor; upset; CMOS technology; Charge measurement; Current measurement; Dielectric thin films; Isolation technology; MOSFETs; Single event upset; Spectroscopy; Testing; Thin film transistors;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.659027

Filename

659027