DocumentCode :
1309126
Title :
Part 1: Logic circuit simulation
Author :
Acken, John M. ; Stauffer, Jerry D.
Author_Institution :
Computer-Aided Design Division 2113, SANDIA LABORATORIES, Albuquerque, New Mexico 87185
Volume :
1
Issue :
1
fYear :
1979
fDate :
3/1/1979 12:00:00 AM
Firstpage :
9
Lastpage :
14
Abstract :
As digital integrated-circuits become more complex, the designer cannot rely on breadboarding but must use a digital computer for circuit simulation to verify correctness of the design. Top-down design, using many simulation levels in a hierarchical structure, is needed for complex systems. Simulation can be used at the Circuit, Logic, RTL, ISP, or Systems Analysis level. To verify the design of a circuit, True-Value Simulation is used. Fault Simulation must be used to determine the proper sequence of test signals used in circuit acceptance after fabrication. A general overview of simulation is given in this first part. A subsequent article will contain a description of a general purpose logic simulation with circuit examples.
Keywords :
Analytical models; Circuit faults; Computational modeling; Integrated circuit modeling; Logic gates; Mathematical model; Transistors;
fLanguage :
English
Journal_Title :
Circuits & Systems Magazine
Publisher :
ieee
ISSN :
0163-6812
Type :
jour
DOI :
10.1109/MCAS.1979.6323670
Filename :
6323670
Link To Document :
بازگشت