Title :
SEU design considerations for MESFETs on LT GaAs
Author :
Weatherford, T.R. ; Radice, R. ; Eskins, D. ; Devers, J. ; Fouts, D.J. ; Marshall, P.W. ; Marshall, C.J. ; Dietrich, H. ; Twigg, M. ; Milano, R.
Author_Institution :
Naval Postgraduate Sch., Monterey, CA, USA
fDate :
12/1/1997 12:00:00 AM
Abstract :
Computer simulation results are reported on transistor design and single-event charge collection modeling of metal-semiconductor field effect transistors (MESFETs) fabricated in the Vitesse H-GaAsIII(R) process on Low Temperature grown (LT) GaAs epitaxial layers. Tradeoffs in Single Event Upset (SEU) immunity and transistor design are discussed. Effects due to active loads and diffusion barriers are examined
Keywords :
III-V semiconductors; Schottky gate field effect transistors; diffusion barriers; digital simulation; gallium arsenide; molecular beam epitaxial growth; radiation effects; semiconductor device models; semiconductor epitaxial layers; semiconductor growth; GaAs; MBE; MESFETs; SEU design considerations; Vitesse H-GaAsIII process; active loads; computer simulation results; diffusion barriers; low temperature grown epitaxial layers; single event upset; single-event charge collection modeling; transistor design; FETs; Gallium arsenide; Implants; Laboratories; Logic devices; MESFETs; Molecular beam epitaxial growth; Semiconductor device modeling; Semiconductor process modeling; Single event upset;
Journal_Title :
Nuclear Science, IEEE Transactions on
