Performance-driven macro-block placer for architectural evaluation of ASIC designs

The authors present a tool for generating a performance-driven placement from a netlist of register-transfer level (RTL) blocks. Based on the modified force-directed algorithm, the tool chooses locations and orientations of the blocks in such a way as to produce a compact area placement with minimum wiring delay along the critical path. Experiments show that the tool provides solutions close to those generated manually, is fast enough to be used in the inner loop of a program which synthesises RTL structures from behavioural specifications and ensures the strong links between RTL synthesis and timing-driven layout which are so necessary for design of submicron ASICs