Title :
Memory Built-in Self Test in Multicore Chips with Mesh-Based Networks
Author :
Liu, Hsiang-Ning ; Huang, Yu-Jen ; Li, Jin-Fu
Author_Institution :
Nat. Central Univ., Jhongli, Taiwan
Abstract :
Using a packet-based built-in self test for RAM cores in mesh-based networks on chip (NoC) can reduce the BIST circuit´s area cost. The proposed scheme reuses the NoC to transport test patterns to RAM such that routing doesn´t limit the number of RAM cores tested. The scheme also achieves higher test parallelism than a typical parallel BIST by interleaving the read/write test operations.
Keywords :
built-in self test; microprocessor chips; network-on-chip; random-access storage; RAM cores; memory built-in self test; mesh-based networks on chip; multicore chips; packet-based built-in self test; Automatic testing; Built-in self-test; Circuit testing; Costs; Interleaved codes; Multicore processing; Network-on-a-chip; Random access memory; Read-write memory; Routing; BIST; march test; multicore; network-on-chip; random access memory; testing.;
Journal_Title :
Micro, IEEE
