• DocumentCode
    1310729
  • Title

    Memory Built-in Self Test in Multicore Chips with Mesh-Based Networks

  • Author

    Liu, Hsiang-Ning ; Huang, Yu-Jen ; Li, Jin-Fu

  • Author_Institution
    Nat. Central Univ., Jhongli, Taiwan
  • Volume
    29
  • Issue
    5
  • fYear
    2009
  • Firstpage
    46
  • Lastpage
    55
  • Abstract
    Using a packet-based built-in self test for RAM cores in mesh-based networks on chip (NoC) can reduce the BIST circuit´s area cost. The proposed scheme reuses the NoC to transport test patterns to RAM such that routing doesn´t limit the number of RAM cores tested. The scheme also achieves higher test parallelism than a typical parallel BIST by interleaving the read/write test operations.
  • Keywords
    built-in self test; microprocessor chips; network-on-chip; random-access storage; RAM cores; memory built-in self test; mesh-based networks on chip; multicore chips; packet-based built-in self test; Automatic testing; Built-in self-test; Circuit testing; Costs; Interleaved codes; Multicore processing; Network-on-a-chip; Random access memory; Read-write memory; Routing; BIST; march test; multicore; network-on-chip; random access memory; testing.;
  • fLanguage
    English
  • Journal_Title
    Micro, IEEE
  • Publisher
    ieee
  • ISSN
    0272-1732
  • Type

    jour

  • DOI
    10.1109/MM.2009.83
  • Filename
    5325155
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1310729