Comparison of Wafer-Level With Package-Level CDM Stress Facilitated by Real-Time Probing

Author

Jack, Nathan ; Shukla, Vrashank ; Rosenbaum, Elyse

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA

Volume

11

Issue

4

fYear

2011

Firstpage

522

Lastpage

530

Abstract

Using real-time voltage probing and circuit simulation, the stress induced by wafer-level charged-device-model (CDM) electrostatic discharge test methods is compared to that of package-level field-induced CDM testers. It is shown that, while wafer-level testers can replicate I/O failures, they may not replicate core failures because of differences in the induced current stress.

Keywords

CMOS integrated circuits; electrostatic discharge; failure analysis; integrated circuit reliability; integrated circuit testing; probes; stress analysis; wafer level packaging; CMOS integrated circuits; I/O failures; circuit simulation; current stress; electrostatic discharge test methods; package-level CDM stress; package-level field-induced CDM testers; real-time voltage probing; wafer-level charged-device-model; wafer-level packaging; CMOS integrated circuits; Current measurement; Electrostatic discharge; Radio frequency; Semiconductor device measurement; Voltage measurement; CMOS integrated circuits (ICs); IC testing; electrostatic discharge (ESD); transmission line measurements;

fLanguage

English

Journal_Title

Device and Materials Reliability, IEEE Transactions on

Publisher

ieee

ISSN

1530-4388

Type

jour

DOI

10.1109/TDMR.2011.2166399

Filename

6006519