1 Gbit/s high-speed bit-synchronisation LSI for B-ISDN

The CCITT recommended that the bit rates for synchronous digital hierarchy (SDH) should be multiples of 155.52 Mbit/s. In handling high-speed data (such as 622.08 Mbit/s) in B-ISDN switching systems, there are problems associated with waveform degradation caused by impedance mismatching and amplitude attenuation. A countermeasure is the regeneration of the distorted waveforms using the system clock in each board. A bit-synchronisation circuit allows distorted waveforms to be regenerated and simplifies the design of timing between boards. The author have developed a high-speed bit-synchronisation LSI with excellent jitter tolerance in the 600 Mbit/s region and which has a simple circuit structure. The LSI features a circuit structure based on an elastic store, Si-bipolar super self-aligned process technology (SST),¹ and careful timing design. It can handle three different bit-rates (622.08, 155.52, and 51.84 Mbit/s) and has a maximum bit rate of 1 Gbit/s.