DocumentCode :
1312395
Title :
A Low-Power Process-Scalable Super-Heterodyne Receiver With Integrated High- 
Filters
Author :
Mirzaei, Ahmad ; Darabi, Hooman ; Murphy, David
Author_Institution :
Broadcom Corp., Irvine, CA, USA
Volume :
46
Issue :
12
fYear :
2011
Firstpage :
2920
Lastpage :
2932
Abstract :
A super-heterodyne receiver utilizing integrated high-Q filters to condition the desired signal to be digitized by a bandpass ADC at an IF of 110 MHz achieves a NF of 2.8 dB and an IIP3 of -8.4 dBm. The conventional M-phase filter is developed to a new form of high-Q filter that is centered at sum or difference of two clocks. The M-phase filter is also evolved to take two quadrature inputs to perform image rejection, while exhibiting a high-Q bandpass response with desired signal located in the center. Built of inverters, switches, and MOS capacitors, the receiver follows technology scaling and is reconfigurable through a clock. The receiver including the dividers and LO path draws 12 mA of battery current and occupies 0.76 mm2 in 65-nm CMOS.
Keywords :
CMOS integrated circuits; MOS capacitors; band-pass filters; invertors; low-power electronics; superheterodyne receivers; switches; CMOS process; M-phase filter; MOS capacitors; bandpass ADC; current 12 mA; frequency 110 MHz; high-Q bandpass response; high-Q filter; image rejection; integrated high-filters; inverters; low-power process-scalable super-heterodyne receiver; noise figure 2.8 dB; size 65 nm; switches; Band pass filters; Baseband filters; Capacitors; Impedance; Radio frequency; Receivers; Bandpass filter; CMOS; N-path filtering; image-rejection filter; impedance transformation; process scalable; receiver; super-heterodyne; zero-IF;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2011.2162909
Filename :
6007062
Link To Document :
