DocumentCode :
1312928
Title :
Easily testable realizations for generalized Reed-Muller expressions
Author :
Sasao, Tsutomu
Author_Institution :
Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Iizuka, Japan
Volume :
46
Issue :
6
fYear :
1997
fDate :
6/1/1997 12:00:00 AM
Firstpage :
709
Lastpage :
716
Abstract :
This paper presents a design method of easily testable AND-EXOR networks. It is an improvement of Reddy (1972) and Saluja-Reddy´s (1975) methods, and has the following features. The network uses generalized Reed-Muller expressions (GRMs) instead of Positive Polarity Reed-Muller expressions (PPRMs). The average number of products for GRMs is less than half of that for PPRMs, and is less than that of sum-of-products expressions (SOPs). The network consists of a literal part, an AND part, an EXOR part, and a check part. The EXOR part can be a tree instead of a cascade. Thus, the network is faster. The test detects multiple stuck at faults under the assumption that the faults occur at most one part, either the literal part, the AND part, the EXOR part, or the check part
Keywords :
Reed-Muller codes; fault location; logic design; logic gates; logic testing; minimisation of switching nets; trees (mathematics); AND; EXOR; Positive Polarity Reed-Muller expressions; cascade; check; circuit complexity; design method; generalized Reed-Muller expressions; linear circuit; logic functions; logic minimization; multiple stuck at faults; sum-of-products expressions; testable AND-EXOR networks; tree; Circuit faults; Circuit testing; Complexity theory; Design methodology; Electrical fault detection; Fault detection; Logic circuits; Logic design; Logic testing; Minimization;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/12.600830
Filename :
600830
Link To Document :
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