Carry-save adders for computing the product AB modulo N

The authors describe a new algorithm for modulator multiplication using carry-save adders. The proposed algorithm is based on the sign-estimation technique. A carry-save adder structure consisting of three rows of n+3 simple 1-bit adder cells, and two copies of 3-bit carry look-ahead logic can be used to implement a single step of the algorithm. A completely pipelined array for modular multiplication designed by cascading n carry-save adders performs modulator multiplication at the clock rate.