Sub-1 V, 4 na CMOS voltage references with digitally-trimmable temperature coefficient

Two architectures for MOS-only low power voltage references with digitally-trimmable temperature coefficient are proposed in this work. A test chip implements them in a 0.35 μm CMOS process. A design methodology for both architectures, performance figures and preliminary test results are presented. Each circuit consumes around 4 nA and operates down to 0.95 V or better with a simulated temperature coefficient of 18 ppm/° C in the -20°C to 80°C range.