Title :
Self-reconfiguring interconnection network for a fault-tolerant mesh-connected array of processors
Author :
Pateras, S. ; Rajski, J.
Author_Institution :
Dept. of Electr. Eng., McGill Univ., Montreal, Que.
fDate :
5/12/1988 12:00:00 AM
Abstract :
An interconnection network capable of spontaneously reconfiguring a mesh-connected processor array on detection of faulty processors is presented. Although the reconfiguration process is global in nature, the network control circuitry is localised around each processor and is therefore completely modular. In addition, the structure of the control circuitry is fixed and thus independent of the array size or the number of spare processors
Keywords :
VLSI; cellular arrays; circuit reliability; logic design; network topology; VLSI array; fault-tolerant mesh-connected array of processors; interconnection network; network control circuitry; spontaneous reconfiguration;
Journal_Title :
Electronics Letters
