Title :
Bit-serial interleaved high speed division
Author :
Marnane, W.P. ; Bellis, S.J. ; Larsson-Edefors, P.
Author_Institution :
Dept. of Electr. Eng. & Microelectron., Univ. Coll. Cork, Ireland
fDate :
6/19/1997 12:00:00 AM
Abstract :
A bit-serial/word-parallel divider circuit with simplified control requirements, is presented. The circuit uses the non-restoring division algorithm which places a restriction on the speed of the circuit. By introducing the concept of bit interleaving, a high speed design can be implemented of the same circuit complexity as an equivalent size multiplier
Keywords :
dividing circuits; bit interleaving; bit-serial word-parallel divider circuit; circuit complexity; control; high speed design; nonrestoring division algorithm;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19970758
