Top-Gated Graphene Field-Effect Transistors Using Graphene on Si (111) Wafers

Author

Moon, J.S. ; Curtis, D. ; Bui, S. ; Marshall, T. ; Wheeler, D. ; Valles, I. ; Kim, S. ; Wang, E. ; Weng, X. ; Fanton, M.

Author_Institution

HRL Labs., LLC, Malibu, CA, USA

Volume

31

Issue

11

fYear

2010

Firstpage

1193

Lastpage

1195

Abstract

In this letter, we report the first experimental demonstration of wafer-scale ambipolar field-effect transistor (FET) on Si (111) substrates by synthesizing a graphene layer on top of 3C-SiC(111)/Si(111) substrates. With lateral scaling of the source-drain distance to 1 μm in a top-gated layout, the ON-state current of 225 μA/μm and peak transconductance of > 40 μS/μm were obtained at Vds = 2 V, which is the highest performance of graphene-on-Si FETs. The peak field-effect mobilities of 285 cm² /Vs for holes and 175 cm² /Vs for electrons were demonstrated, which is higher than that of ultra-thin-body SOI (n, p) MOSFETs.

Keywords

MOSFET; field effect transistors; graphene; silicon-on-insulator; MOSFET; source-drain distance; top-gated graphene; ultra-thin-body SOI; wafer-scale ambipolar field-effect transistor; Epitaxial growth; Logic gates; Metals; Silicon; Substrates; Transconductance; Transistors; Field-effect mobility; SOI MOSFET; Si MOSFET; field-effect transistor (FET); graphene; n-FET; p-FET;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2010.2065792

Filename

5565389