Title :
Fault modelling of ECL devices
Author :
Menon, S.M. ; Jayasumona, A.P.
Author_Institution :
Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA
fDate :
7/19/1990 12:00:00 AM
Abstract :
Logic behaviour of an ECL OR/NOR gate under different physical faults is examined. It is shown that the conventional stuck-at fault modelling may be inadequate for obtaining a sufficiently high fault coverage. A new augmented stuck-at fault model is presented which provides a better coverage of physical failures.
Keywords :
emitter-coupled logic; fault location; logic gates; ECL devices; OR/NOR gate; augmented stuck-at fault model; fault coverage; physical faults; stuck-at fault modelling;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19900715
