Energy-Efficient Joint Scheduling and Application-Specific Interconnection Design

Energy-efficient and high-performance interconnections are critical for multiprocessor architectures. As technology moves into deep submicrometer level, static and dynamic energy consumptions have become dominant constraint factors in high-performance system design. This paper jointly considers scheduling and interconnection design to minimize the interconnection´s energy consumption without performance degradation. The Interconnection Energy Minimization Scheduling algorithm is proposed in this paper to design interconnection with segmented buses and to determine a feasible computation and communication schedule to minimize interconnection´s energy consumption while meeting tight-latency and high-volume data transfer needs for applications with large inherited parallelism. Experimental results show that interconnection´s dynamic energy consumption can be reduced by about 71% and static energy consumption can be reduced by about 35% on average when the proposed algorithm is compared with existing communication cost-conscious scheduling techniques for the evaluated digital signal processing and media applications.