DocumentCode
1315882
Title
Optimised design for a 0.5 mu m gate length n-channel SOI MOSFET
Author
Armstrong, G.A. ; French, William D.
Author_Institution
Dept. of Electr. Eng., Queen´s Univ. of Belfast, UK
Volume
26
Issue
15
fYear
1990
fDate
7/19/1990 12:00:00 AM
Firstpage
1196
Lastpage
1198
Abstract
Two dimensional device simulation has been used to optimise the design of an n-channel silicon-on-insulator MOSFET with an ultra thin film. The trade-off between SOI film thickness and film doping on the threshold voltage, inverse subthreshold slope and breakdown voltage is considered. The effect of carrier lifetime on the breakdown voltage is described. Use of a lightly doped drain gives a simulated breakdown voltage greater than 3..5 V for a transistor with a film thickness of 1000 AA and a gate length of 0.5 mu m.
Keywords
carrier lifetime; insulated gate field effect transistors; semiconductor device models; semiconductor-insulator boundaries; 0.5 micron; 2-D device simulation; SOI film thickness; breakdown voltage; carrier lifetime; film doping; gate length; inverse subthreshold slope; lightly doped drain; n-channel SOI MOSFET; n-channel silicon-on-insulator MOSFET; simulated breakdown voltage; threshold voltage;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19900774
Filename
82944
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