Algorithm for optimal layouts of CMOS complex logic modules

A new algorithm which finds the optimal layout of CMOS complex logic modules from the given Boolean logic expressions is described . The problem of minimising the layout area of static CMOS logic module is converted to the problem of determining the graph model structure for each subcircuit of the given logic circuit and merging all subgraphs in all possible ways to find the optimal solution being characterised by the minimum number of subgraphs each having a dual Euler trail.