Impacts of Poly-Si Nanowire Shape on Gate-All-Around Flash Memory With Hybrid Trap Layer

Author

Hung-Bin Chen ; Yung-Chun Wu ; Chao-Kan Yang ; Lun-Chun Chen ; Ji-Hong Chiang ; Chun-Yen Chang

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

32

Issue

10

fYear

2011

Firstpage

1382

Lastpage

1384

Abstract

This letter demonstrates the shape effect of suspended poly-Si nanowires (NWs) on gate-all-around TFT Flash memory. The NWs are bent into a bimodal shape by process-induced strain. The proposed dual-gate (DG) and single-gate (SG) electrodes are located on the twin peaks and single valley of the bimodal shape of the NWs. The DG structure has better program/erase characteristics and reliability than the SG structure owing to the impact of the bent NWs on the dielectric strength of tunnel oxide. Moreover, incorporation of the hybrid trap layer in the DG device yields a long retention time, with only 17% charge loss over ten years.

Keywords

electric strength; electrodes; elemental semiconductors; flash memories; nanowires; semiconductor device models; semiconductor device reliability; silicon; thin film transistors; bimodal shape; dielectric strength; dual-gate electrode; gate-all-around TFT flash memory; hybrid trap layer; poly-Si nanowire shape; process-induced strain; program-erase characteristic; single-gate electrode; tunnel oxide; Electric breakdown; Flash memory; Logic gates; Shape; Silicon; Thin film transistors; Flash memory; gate-all-around (GAA); nanowire (NW); thin-film transistor (TFT);

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2011.2161257

Filename

6012512