New analogue four-quadrant voltage divider

A new circuit structure for the realisation of an analogue four-quadrant voltage divider with improved dynamic performance is proposed. The structure was developed on the basis of the augmented Lagrangian method and the gradient optimisation approach. The circuit is especially suited for monolithic IC implementation by employing the CMOS switched-capacitor (SC) techniques. The device has been built using SC discrete components and also simulated on computer. Experimental test and computer simulation results have confirmed the theoretical predictions, especially the dynamic error reduction of the device.