DocumentCode
1316584
Title
Low-power CMOS current conveyor
Author
Ismail, Abdul Manaff ; Soliman, A.M.
Author_Institution
Dept. of Electron. & Commun. Eng., Cairo Univ., Giza, Egypt
Volume
36
Issue
1
fYear
2000
fDate
1/6/2000 12:00:00 AM
Firstpage
7
Lastpage
8
Abstract
A novel second-generation CMOS current conveyor based on a new adaptive biasing technique is proposed. It is shown that the use of this circuit offers an excellent performance and leads to a significant reduction in the standby power dissipation. PSPICE simulation results, assuming 0.5 μm CMOS process, are also given
Keywords
CMOS analogue integrated circuits; 0.5 micron; PSPICE simulation results; adaptive biasing technique; low-power electronics; second-generation CMOS current conveyor; standby power dissipation;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20000129
Filename
830482
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