• DocumentCode
    1316663
  • Title

    3–5 GHz 4-Channel UWB Beamforming Transmitter With 1 ^{\\circ} Scanning Resolution Through Calibrated Vernier Delay Line in 0.13-

  • Author

    Wang, Lei ; Lian, Yong ; Heng, Chun-Huat

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore, Singapore
  • Volume
    47
  • Issue
    12
  • fYear
    2012
  • Firstpage
    3145
  • Lastpage
    3159
  • Abstract
    A 3-5 GHz 4-channel UWB beamforming transmitter with 1° scanning resolution and 135° scanning range is presented in this paper. The fine resolution is attained through Vernier delay lines capable of fine resolution down to 10 ps. Accurate path delay across channels as well as UWB pulse center frequency are achieved through the proposed ΔΣ DLL calibration technique, which speeds up the calibration by 48 times compared with a counter-based approach. A novel power spectral density calibration circuit is included to adjust the UWB pulse shape for meeting the FCC mask. Fabricated in 0.13-μm CMOS, the proposed transmitter occupies only 7.2 mm2. The power consumption is 9.6 mW while transmitting at 80 Mbps, with each transmitter achieving 10 pJ/bit and transmitter efficiency of 7.5%. This is about ten times better than those existing UWB beamforming transmitters.
  • Keywords
    CMOS integrated circuits; delay lock loops; low-power electronics; radio transmitters; ultra wideband communication; wireless channels; ΔΣ DLL calibration technique; 4-channel UWB beamforming transmitter; CMOS; FCC mask; UWB pulse center frequency; bit rate 80 Mbit/s; calibrated Vernier delay line; frequency 3 GHz to 5 GHz; power 9.6 mW; power consumption; power spectral density calibration circuit; size 0.13 mum; Array signal processing; Calibration; Computer architecture; Delay lines; Microprocessors; Transmitters; $DeltaSigma$ DLL; All-digital UWB transmitter; PSD calibration circuit; UWB beamforming transmitter; Vernier delay line; beamforming delay chain;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.2012.2216704
  • Filename
    6329989