High-speed and low-power reconfigurable architectures of 2-digit two-dimensional logarithmic number system-based recursive multipliers

In new DSP applications, reconfigurable architectures have emerged to provide a flexible, high-performance, high-speed and low-power implementation platform for wireless embedded devices. Since some DSP algorithms rely heavily on multiplication, there are still demands for more efficient multiplication structures. In this study, two reconfigurable recursive multipliers are presented. The authors´ architectures combine some of the flexibility of software with the high performance of hardware through implementing different levels of recursive multiplication schemes on a two-dimensional logarithmic number system (2DLNS) processing structure. The data are split into a number of smaller sections, where each section is converted to a 2-digit 2DLNS (2 bases) representation. The dynamic range reduction and logarithmic characteristics of computing with two orthogonal base exponents in this number system allows multiplication to be implemented with simple parallel small adders. The authors´ architectures are able to perform single and double precision multiplications, as well as fault tolerant and dual throughput single precision operations. The implementations demonstrate the efficiency of 2DLNS in multiplication intensive DSP applications and show outstanding results in terms of operation delay and dynamic power consumption.