• DocumentCode
    1317148
  • Title

    Alternative algorithm for optimisation of Reed-Muller universal logic module networks

  • Author

    Tan, E.C. ; Chia, C.Y.

  • Author_Institution
    Div. of Comput. Eng., Nanyang Technol. Univ., Singapore
  • Volume
    143
  • Issue
    6
  • fYear
    1996
  • fDate
    11/1/1996 12:00:00 AM
  • Firstpage
    385
  • Lastpage
    390
  • Abstract
    Reed-Muller universal logic modules (RM-ULMs) can be used as individual modules or as networks to implement RM functions of any number of variables. For a large RM expansion, it is generally more efficient to realise it using cascades of low-order RM-ULMs. A programmed algorithm for the optimisation of the number of modules at the sub-system level has already been published. In the paper an alternative algorithm is presented which performs similar optimisation of fixed-polarity generalised RM expansions but without the need to maintain a saved-branch counter and an input record. Also, whenever the number of piterms having the specific control-tuple-state exceeds two, it is not necessary for the algorithm to perform separate variable examinations. Consequently, the saving in computation time will be especially significant in RM expansions with large number of variables. The resulting algorithm is simple in structure and can be easily implemented using high-level languages such as C or Fortran
  • Keywords
    Boolean functions; circuit optimisation; computational complexity; logic CAD; switching functions; Boolean function; C language; Fortran; RM expansion; RM functions; Reed-Muller universal logic module network optimisation; computation time; control-tuple-state; fixed-polarity generalised RM expansions; high-level languages; input record; saved-branch counter; sub-system level;
  • fLanguage
    English
  • Journal_Title
    Computers and Digital Techniques, IEE Proceedings -
  • Publisher
    iet
  • ISSN
    1350-2387
  • Type

    jour

  • DOI
    10.1049/ip-cdt:19960770
  • Filename
    556709