A closed-form back-gate-bias related inverse narrow-channel effect model for deep-submicron VLSI CMOS devices using shallow trench isolation

Author

Lin, Shih-Chia ; Kuo, James B. ; Huang, Kuo-Tai ; Sun, Shih-Wei

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

47

Issue

4

fYear

2000

fDate

4/1/2000 12:00:00 AM

Firstpage

725

Lastpage

733

Abstract

This paper reports an analytical inverse narrow-channel effect threshold voltage model for shallow-trench-isolated (STI) CMOS devices using a conformal mapping technique to simplify the two-dimensional (2-D) analysis. As verified by the experimentally measured data and the 2-D simulation results, the analytical model predicts well the inverse narrow-channel effect threshold voltage behavior of the STI CMOS devices. Based on the study, the inverse narrow-channel effect also affects the saturation-region output conductance of a small geometry STI CMOS device in addition to the short-channel effect

Keywords

CMOS integrated circuits; MOSFET; VLSI; integrated circuit modelling; isolation technology; semiconductor device models; 2D simulation; closed-form back-gate-bias related; conformal mapping technique; deep-submicron VLSI CMOS devices; electrostatic potential; inverse narrow-channel effect model; saturation-region output conductance; shallow trench isolation; threshold voltage model; Analytical models; CMOS technology; Conformal mapping; Inverse problems; Isolation technology; MOS devices; Semiconductor device modeling; Sun; Threshold voltage; Very large scale integration;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.830986

Filename

830986