• DocumentCode
    1317565
  • Title

    Note on optimal tile partition for space region of integrated-circuit geometry

  • Author

    Ku, L.-P. ; Leong, H.W.

  • Author_Institution
    Dept. of Inf. Syst. & Comput. Sci., Nat. Univ. of Singapore, Singapore
  • Volume
    143
  • Issue
    4
  • fYear
    1996
  • fDate
    7/1/1996 12:00:00 AM
  • Firstpage
    246
  • Lastpage
    248
  • Abstract
    An OTP algorithm for solving the optimal tile-partitioning problem has recently been published by P.Y. Hsiao et al. (1993). The OTP algorithm makes use of an elimination algorithm to find a maximum set of nonintersecting critical partition edges. It is shown that this elimination algorithm is flawed
  • Keywords
    VLSI; circuit layout CAD; computational geometry; elimination algorithm; integrated-circuit geometry; optimal tile partition; space region;
  • fLanguage
    English
  • Journal_Title
    Computers and Digital Techniques, IEE Proceedings -
  • Publisher
    iet
  • ISSN
    1350-2387
  • Type

    jour

  • DOI
    10.1049/ip-cdt:19960563
  • Filename
    532859
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1317565