A physical thermal noise model for SOI MOSFET

Author

Jin, Wei ; Chan, Philip C.H. ; Lau, Jack

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ., Hong Kong

Volume

47

Issue

4

fYear

2000

fDate

4/1/2000 12:00:00 AM

Firstpage

768

Lastpage

773

Abstract

The recent progress in SOI technology necessitates an accurate thermal noise model for wide-band SOI analog IC design. In this paper a physical-based thermal noise model is proposed for floating-body SOI MOSFET operated in strong inversion regime and verified by the experimental data. In the model, both the lattice temperature (unique to SOI due to the buried oxide) and the carrier temperature (significant for short-channel device in saturation region) are considered. The model agrees well with the experimental data

Keywords

MOSFET; equivalent circuits; semiconductor device models; semiconductor device noise; silicon-on-insulator; thermal noise; SOI MOSFET; Si; buried oxide; carrier temperature; floating-body SOI device; lattice temperature; physical thermal noise model; saturation region; short-channel device; strong inversion regime; wideband SOI analog IC design; Analog integrated circuits; CMOS technology; Integrated circuit modeling; Integrated circuit noise; Lattices; MOSFET circuits; Semiconductor device modeling; Silicon on insulator technology; Temperature; Wideband;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.830992

Filename

830992