FRAM cell design with high immunity to fatigue and imprint for 0.5 μm 3 V 1T1C 1 Mbit FRAM

Author

Tanaka, Sumio ; Ogiwara, Ryu ; Itoh, Yasuo ; Miyakawa, Tadeshi ; Takeuchi, Yoshiaki ; Doumae, Sumiko ; Takenaka, Hiroyuki ; Kamata, Hideyuki

Author_Institution

ULSI Device Eng. Lab., Toshiba Corp., Yokohama, Japan

Volume

47

Issue

4

fYear

2000

fDate

4/1/2000 12:00:00 AM

Firstpage

781

Lastpage

788

Abstract

A new ferroelectric random access memory (FRAM) cell design with high immunity to fatigue and imprint has been proposed in order to achieve a megabit class FRAM with 1T1C cell structure, and has been applied to a 1 M bit FRAM operated from a 3(V) supply with 1T1C cell structure, 0.5(μm) rule and 3(μm²) capacitor area. The simulation result and imprint data predict a seven order imprint lifetime improvement compared with the conventional scheme. A pseudo after PL pulse scheme has also been presented to accelerate the slow read/write cycle time of after PL pulse

Keywords

cellular arrays; ferroelectric storage; integrated memory circuits; random-access storage; 0.5 micron; 1T1C cell structure; 3 V; FRAM cell; capacitor area; cell design; fatigue immunity; ferroelectric random access memory; imprint immunity; imprint lifetime; pseudo after PL pulse scheme; read/write cycle time; Acceleration; Capacitors; Fatigue; Ferroelectric films; Ferroelectric materials; Nonvolatile memory; Predictive models; Pulse amplifiers; Random access memory; Voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.830994

Filename

830994