DocumentCode
1318001
Title
On-chip signature analyser for analogue circuit testing
Author
Renovell, M. ; Azaïs, F. ; Bertrand, Y.
Author_Institution
LIRMM, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
Volume
32
Issue
24
fYear
1996
fDate
11/21/1996 12:00:00 AM
Firstpage
2185
Lastpage
2186
Abstract
The authors propose a technique for on-chip analogue response compaction to implement self-test capabilities in analogue circuits. The integration function is identified as a powerful analogue compression scheme and op-amp-based implementations are proposed for both single and multiple-input analysers. Validations show that an improved fault coverage can be achieved
Keywords
analogue integrated circuits; built-in self test; integrated circuit testing; operational amplifiers; BIST; analogue ICs; analogue circuit testing; analogue compression scheme; analogue response compaction; fault coverage improvement; multiple-input analysers; onchip signature analyser; op-amp-based implementations; self-test capabilities; single-input analysers;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19961511
Filename
556743
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