Title :
On the design of fast, easily testable ALU´s
Author :
Blanton, R.D. ; Hayes, John P.
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
fDate :
4/1/2000 12:00:00 AM
Abstract :
A design methodology for implementing fast, easily testable arithmetic-logic units (ALUs) is presented. Here, we describe a set of fast adder designs, which are testable with a test set that has either /spl theta/(N) complexity (Lin-testable) or /spl theta/(1) complexity (C-testable), where N is the input operand size of the ALU. The various levels of testability are achieved by exploiting some inherent properties of carry-lookahead addition. The Lintestable and C-testable ALU designs require only one extra input, regardless of the size of the ALU. The area overhead for a high-speed 64-bit Lintestable ALU is only 0.5%.
Keywords :
adders; carry logic; computational complexity; design for testability; fault diagnosis; logic CAD; /spl theta/(1) complexity; /spl theta/(N) complexity; 64 bit; C-testable designs; Lintestable designs; adder designs; area overhead; arithmetic-logic units; carry-lookahead addition; design methodology; input operand size; testability; Adders; Circuit faults; Circuit noise; Circuit testing; Design methodology; Logic arrays; Metastasis; Solid state circuits; Synchronization; Very large scale integration;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
