Zero-Crossing Detector Based Reconfigurable Analog System

Author

Lajevardi, Payam ; Chandrakasan, Anantha P. ; Lee, Hae-Seung

Author_Institution

Massachusetts Inst. of Technol. (MIT), Cambridge, MA, USA

Volume

46

Issue

11

fYear

2011

Firstpage

2478

Lastpage

2487

Abstract

A reconfigurable analog system is presented that implements pipelined ADCs, switched-capacitor filters, and programmable gain amplifiers. Each block employs a zero-crossing based circuit for easy reconfigurability and power efficiency. Configured as a 10-bit ADC, the chip consumes 1.92 mW at 50 MSPS with ENOB of 8.02 bit and FOM of 150 fJ/conversion-step. A second-order and a third-order Butterworth filter are also demonstrated. The thermal noise of the system is analyzed in different configurations and the dominant sources of noise are determined. It is shown that around 90% of the noise in ADC configuration is generated by the first stage, while in filter configuration, around 90% of the noise is generated by the last stage. The chip is implemented in a 65 nm technology.

Keywords

Butterworth filters; amplifiers; analogue-digital conversion; field programmable analogue arrays; switched capacitor filters; thermal noise; FPAA; field programmable analog array; noise dominant source; pipelined ADC implementation; power 1.92 mW; programmable gain amplifier; reconfigurable analog system; second-order Butterworth filter; size 65 nm; switched-capacitor filter; thermal noise; third-order Butterworth filter; word length 10 bit; word length 8.02 bit; zero-crossing based circuit; zero-crossing detector; Capacitors; Detectors; Noise; Power demand; Resistors; Switches; Thermal noise; Analog FPGA; analog to digital convertor; ladder filter; pipeline ADC; programmable analog array; reconfigurable analog; switched capacitor circuit; zero-crossing circuit;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2011.2164295

Filename

6017144