• DocumentCode
    1319073
  • Title

    Assertion Aware Sampling Refinement: A Mixed-Signal Perspective

  • Author

    Mukherjee, Sayan ; Dasgupta, Parthasarathi

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Indian Inst. of Technol. Kharagpur, Kharagpur, India
  • Volume
    31
  • Issue
    11
  • fYear
    2012
  • Firstpage
    1772
  • Lastpage
    1776
  • Abstract
    Sampling has been one of the key issues in simulation-based verification of analog and mixed signal (AMS) systems. Recent attempts toward extending assertion languages to the AMS domain has brought forward an obvious question. In what way should sampling be done to ensure that assertions are evaluated correctly? Increasing sampling granularity often comes with substantial simulation time overhead. On the other hand, interpolation of the analog signals between consecutive samples introduces inaccuracies in the signal values and, hence, in the truth of the assertions. This paper explores how temporal assertions are handled for inadequately sampled signals. We propose a three-valued semantics (true, false, and unknown) for AMS assertions to address the uncertainty caused by the inadequacy of samples. The evaluation algorithm reports the time intervals where additional samples are required to resolve the uncertainty, thereby paving the way for adaptive sampling refinement in assertion aware AMS simulation.
  • Keywords
    formal verification; hardware description languages; mixed analogue-digital integrated circuits; AMS assertions; AMS domain; adaptive sampling refinement; assertion aware AMS simulation; assertion aware sampling refinement; assertion languages; mixed signal systems; mixed-signal perspective; sampling granularity; simulation-based verification; three-valued semantics; Hardware design languages; Integrated circuit modeling; Monitoring; Phase locked loops; Robustness; Semantics; Uncertainty; Real-time temporal logic; sampling; simulation;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2012.2202394
  • Filename
    6331650