Title :
Upset hardened memory design for submicron CMOS technology
Author :
Calin, T. ; Nicolaidis, M. ; Velazco, R.
Author_Institution :
TIMA/INPG Lab., Grenoble, France
fDate :
12/1/1996 12:00:00 AM
Abstract :
A novel design technique is proposed for storage elements which are insensitive to radiation-induced single-event upsets. This technique is suitable for implementation in high density ASICs and static RAMs using submicron CMOS technology
Keywords :
CMOS memory circuits; SRAM chips; application specific integrated circuits; integrated circuit design; radiation hardening (electronics); high density ASIC; memory design; radiation hardening; single-event upsets; static RAM; storage element; submicron CMOS technology; CMOS process; CMOS technology; Delay; Feedback circuits; Image storage; Laboratories; Latches; Power dissipation; Single event upset; Space technology;
Journal_Title :
Nuclear Science, IEEE Transactions on
